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w9864g2gh 512k x 4 banks x 32bits sdram publication release date:jan. 29, 2008 - 1 - revision a10 table of contents- 1. general description ......................................................................................................... 3 2. features ................................................................................................................................. 3 3. available part number ...................................................................................................... 4 4. pin configuration ............................................................................................................... 5 5. pin description ..................................................................................................................... 6 6. block diagram ...................................................................................................................... 7 7. functional description .................................................................................................... 8 7.1 power up and initialization ............................................................................................. 8 7.2 programming mode register .......................................................................................... 8 7.3 bank activate command ................................................................................................ 8 7.4 read and write access modes ...................................................................................... 8 7.5 burst read command .................................................................................................... 9 7.6 burst command .............................................................................................................. 9 7.7 read interrupted by a read ........................................................................................... 9 7.8 read interrupted by a write ............................................................................................ 9 7.9 write interrupted by a write ............................................................................................ 9 7.10 write interrupted by a read ............................................................................................ 9 7.11 burst stop command ................................................................................................... 10 7.12 addressing sequence of sequential mode .................................................................. 10 7.13 addressing sequence of interleave mode .................................................................... 10 7.14 auto-precharge command ........................................................................................... 11 7.15 precharge command .................................................................................................... 11 7.16 self refresh command ................................................................................................ 11 7.17 power down mode ....................................................................................................... 12 7.18 no operation command ............................................................................................... 12 7.19 deselect command ...................................................................................................... 12 7.20 clock suspend mode .................................................................................................... 12 8. operation mode ................................................................................................................. 13 8.1 simplified stated diagram ............................................................................................ 14 9. electrical characteristics ......................................................................................... 15 9.1 absolute maximum ratings .......................................................................................... 15
w9864g2gh publication release date:jan. 29, 2008 - 2 - revision a10 9.2 recommended dc operating conditions .................................................................... 15 9.3 capacitance .................................................................................................................. 16 9.4 dc characteristics ........................................................................................................ 16 9.5 ac characteristics and operating condition ................................................................ 17 10. timing waveforms ............................................................................................................. 20 10.1 command input timing ................................................................................................ 20 10.2 read timing .................................................................................................................. 21 10.3 control timing of input data ......................................................................................... 22 10.4 control timing of output data ...................................................................................... 23 10.5 mode register set cycle .............................................................................................. 24 11. operating timing example ............................................................................................. 25 11.1 interleaved bank read (burst length = 4, cas latency = 3) ...................................... 25 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) ........... 26 11.3 interleaved bank read (burst length = 8, cas latency = 3) ...................................... 27 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) ........... 28 11.5 interleaved bank write (burst length = 8) ................................................................... 29 11.6 interleaved bank write (burst length = 8, auto-precharge) ........................................ 30 11.7 page mode read (burst length = 4, cas latency = 3) ............................................... 31 11.8 page mode read/write (burst length = 8, cas latency = 3) ..................................... 32 11.9 auto-precharge read (burst length = 4, cas latency = 3) ........................................ 33 11.10 auto-precharge write (burst length = 4) .................................................................... 34 11.11 auto refresh cycle ..................................................................................................... 35 11.12 self refresh cycle ....................................................................................................... 36 11.13 bust read and single write (burst length = 4, cas latency = 3) ............................. 37 11.14 power down mode ...................................................................................................... 38 11.15 auto-precharge timing (write cycle) .......................................................................... 39 11.16 auto-precharge timing (read cycle) .......................................................................... 40 11.17 timing chart of read to write cycle ........................................................................... 41 11.18 timing chart of write to read cycle ........................................................................... 41 11.19 timing chart of burst stop cycle (burst stop command) .......................................... 42 11.20 timing chart of burst stop cycle (precharge command) .......................................... 42 11.21 cke/dqm input timing (write cycle) ......................................................................... 43 11.22 cke/dqm input timing (read cycle) ......................................................................... 44 12. package specification .................................................................................................... 45 12.1 86l tsop (ii)-400 mil ................................................................................................... 45 13. revision history ................................................................................................................ 46
w9864g2gh 512k x 4 banks x 32bits sdram publication release date:jan. 29, 2008 - 3 - revision a10 1. general description w9864g2gh is a high-speed synchronous dynamic random access memory (sdram), organized as 512k words 4 banks 32 bits. using pipelined architecture and 0.11 m process technology, w9864g2gh delivers a data bandwidth of up to 800m bytes per second. for different application, w9864g2gh is sorted into the following speed grade s:-5,-6/-6c/-6i,-7.the -5 parts can run up to 200mhz/cl3.the -6/-6c/-6i parts can run up to 166 mhz/cl3. and the grade of ?6c with t ck =7.5ns on cl=2, t ih =0.8ns on cl=2/3.and the -6i grade which is guaranteed to support -40c ~ 85c.the -7 parts can run up to 143 mhz/cl3. accesses to the sdram are burst oriented. c onsecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically gener ated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving amon g internal banks to hide the precharging time. by having a programmable mode register, the syst em can change burst length, latency cycle, interleave or sequential burst to maximize its performance. w9864g2gh is ideal for main memory in high performance applications. 2. features ? 3.3v 0.3v for -5/-6/-6 c/-6i grade power supply 2.6v 3.6v for -7 grade power supply ? 524,288 words 4 banks 32 bits organization ? self refresh current: standard and low power ? cas latency: 2 & 3 ? burst length: 1, 2, 4, 8 and full page ? sequential and interleave burst ? byte data controlled by dqm0-3 ? auto-precharge and controlled precharge ? burst read, single write operation ? 4k refresh cycles/64 ms ? interface: lvttl ? packaged in tsop ii 86-pin, 400 mil ? w9864g2gh is using lead free materials
w9864g2gh publication release date:jan. 29, 2008 - 4 - revision a10 3. available part number part number speed (cl=3) self refresh current (max.) operating temperature w9864g2gh-5 200 mhz 2ma 0 c ~ 70 c w9864g2gh-6/-6c 166 mhz 2ma 0 c ~ 70 c W9864G2GH-6I 166 mhz 2ma -40 c ~ 85 c w9864g2gh-7 143 mhz 2ma 0 c ~ 70 c
w9864g2gh publication release date:jan. 29, 2008 - 5 - revision a10 4. pin configuration 86 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 37 38 39 40 41 42 43 28 29 30 31 32 33 34 35 36 50 49 48 47 46 45 44 58 57 56 55 54 53 52 51 85 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v cc q dq30 dq29 v ss q dq28 dq27 v cc q dq26 dq25 v ss q dq24 v ss vcc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 vssq dq7 nc vcc dqm0 we cas ras cs nc bs0 bs1 a10/ap a0 a1 a2 dqm2 v cc nc dq16 v ss q dq17 dq18 v cc q dq19 dq20 v ss q dq21 dq22 v cc q dq23 v cc
w9864g2gh publication release date:jan. 29, 2008 - 6 - revision a10 5. pin description pin number pin name function description 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 a0 ? a10 address multiplexed pins for row and column address. row address: a0 ? a10. column address: a0 ? a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. 22, 23 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 dq0 ? dq31 data input/ output multiplexed pins for data output and input. 20 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 19 ras row address strobe command input. when sampled at the rising edge of the clock ras , cas and we define the operation to be executed. 18 cas column address strobe referred to ras 17 we write enable referred to ras 16, 28, 59, 71 dqm0 ? dqm3 input/output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. 68 clk clock inputs system clock used to sample inputs on the rising edge of clock. 67 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 1, 15, 29, 43 v cc power power for input buffers and logic circuit inside dram. 44, 58, 72, 86 v ss ground ground for input buffers and logic circuit inside dram. 3, 9, 35, 41, 49, 55, 75, 81 v ccq power for i/o buffer separated power from vcc, to improve dq noise immunity. 6, 12, 32, 38, 46, 52, 78, 84 v ssq ground for i/o buffer separated ground from vss, to improve dq noise immunity. 14, 21, 30, 57, 69, 70, 73 nc no connection no connection.(the nc pin must connect to ground or floating.)
w9864g2gh publication release date:jan. 29, 2008 - 7 - revision a10 6. block diagram dq0 dq31 dqm0~3 clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 2048 * 256 * 32 row decoder row decoder row decoder row decoder a0 a9 bs0 bs1 cs ras cas we
w9864g2gh publication release date:jan. 29, 2008 - 8 - revision a10 7. functional description 7.1 power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guar antee the device being preconditioned to each user specific needs. during power up, all v cc and v ccq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the ?nop? st ate. the power up voltage must not exceed vcc + 0.3v on any of the input pins or vcc supplies. after power up, an initial pause of 200 s is required followed by a precharge of all banks using the precharge co mmand. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode re gister set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. 7.2 programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke mu st be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode regi ster set command once a delay equal to t rsc has elapsed. please refer to the next page for mo de register set cycle and operation table. 7.3 bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras activate in ed o dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is det ermined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). 7.4 read and write access modes after a bank has been activated, a read or write cy cle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the acce ss and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
w9864g2gh publication release date:jan. 29, 2008 - 9 - revision a10 7.5 burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of the clock. the add ress inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the mode regi ster set up cycle. table 2 and 3 in the next page explain the address sequence of in terleave mode and sequence mode. 7.6 burst command the burst write command is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaini ng data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. 7.7 read interrupted by a read a burst read may be interrupted by another read co mmand. when the previous burst is interrupted, the remaining addresses are overrid den by the new read address with the full burst length. the data from the first read command continues to appea r on the outputs until the cas latency from the interrupting read command the is satisfied. 7.8 read interrupted by a write to interrupt a burst read with a write comm and, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. 7.9 write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addr esses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 write interrupted by a read a read command will interrupt a burst write operat ion on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at l east one cycle before the new read data appears on the outputs to avoi d data contention. when the read command is activated, any residual data from t he burst write cycl e will be ignored.
w9864g2gh publication release date:jan. 29, 2008 - 10 - revision a10 7.11 burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance st ate after a delay, which is equal to the cas latency in a burst read cycle, interrupted by burst stop. 7.12 addressing sequence of sequential mode a column access is performed by increasing the addr ess from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2 . table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 7.13 addressing sequence of interleave mode a column access is started in the input column add ress and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a 0 data 2 a8 a7 a6 a5 a4 a3 a2 a 1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a 1 a 0 data 4 a8 a7 a6 a5 a4 a3 a 2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a 2 a1 a 0 data 6 a8 a7 a6 a5 a4 a3 a 2 a 1 a0 data 7 a8 a7 a6 a5 a4 a3 a 2 a 1 a 0
w9864g2gh publication release date:jan. 29, 2008 - 11 - revision a10 7.14 auto-precharge command if a10 is set to high when the read or write command is issued, then the auto-precharge function is entered. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain nu mber of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. therefor e, use of a read, write, or precharge command is prohibited during a read or write cycle with auto-precharge. once the precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto- precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation two cloc ks delay from the last burst writ e cycle. this delay is referred to as write t wr . the bank undergoing auto-precharge cannot be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data-in to active delay (t dal = t wr + t rp ). when using the auto- precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras (min). 7.15 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0 and bs1 are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). 7.16 self refresh command the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operati on and before the next command can be issued. this delay is equal to the t ac cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 au to refresh cycles should be completed just prior to entering and just after exiting the self refresh mode.
w9864g2gh publication release date:jan. 29, 2008 - 12 - revision a10 7.17 power down mode the power down mode is initiated by holding cke lo w. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing c ke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t ces (min.) + t ck (min.). 7.18 no operation command the no operation command should be used in cases w hen the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas and we signals become don?t cares. 7.20 clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation t hat was currently being executed. there is a one clock delay between the registrati on of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bri nging cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited.
w9864g2gh publication release date:jan. 29, 2008 - 13 - revision a10 8. operation mode fully synchronous operations are performed to la tch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1), (2)) command device state cken-1 cken dqm bs0, 1 a10 a0-a9 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto-precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto-precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto-refresh idle h h x x x x l l l h self-refresh entry idle h l x x x x l l l h self refresh exit idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x h clock suspend mode exit acti ve l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x h data write/output enable ac tive h x l x x x x x x x data write/output disable active h x h x x x x x x x notes : (1) v = valid, x = don?t care, l = low level, h = high level (2) cken signal is input leve l when commands are provided. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
w9864g2gh publication release date:jan. 29, 2008 - 14 - revision a10 8.1 simplified stated diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke s e l f s e l f e x i t c k e c k e w r i t e w i t h read write a u t o p r e c h a r g e a u t o p r e c h a r g e r e a d w i t h write w r i t e r e a d p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) read b s t b s t pre manual input automatic sequence mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto-precharge reada = read with auto-precharge
w9864g2gh publication release date:jan. 29, 2008 - 15 - revision a10 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit notes input, column output voltage v in , v out -0.3~ vcc + 0.3v v 1 power supply voltage vcc , vcc q -0.3~4.6v v 1 operating temperature t opr 0 ~ 70 c 1 operating temperature (-6i) t opr -40 ~ 85 c 1 storage temperature t stg -55 ~ 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 9.2 recommended dc operating conditions (t a = 0 to 70 c for -5/-6/-6c/-7, t a = -40 to 85 c for -6i ) parameter sym. min. typ. max. unit notes power supply voltage vcc 3.0 3.3 3.6 v power supply voltage (for i/o buffer) vcc q 3.0 3.3 3.6 v power supply voltage(-7) vcc 2.6 3.3 3.6 v power supply voltage (for i/o buffer)(-7) vcc q 2.6 3.3 3.6 v input high voltage v ih 2 - vcc +0.3 v 1 input low voltage v il -0.3 - +0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i i (l) -10 - 10 a 3 output leakage current i o (l) -10 - 10 a 4 note : 1. v ih (max.) = v cc /v ccq +1.2v for pulse width < 5 ns 2. v il (min.) = v ss /v ssq -1.2v for pulse width < 5 ns 3. any input 0v < v in < v ccq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. output disabled, 0v v out v ccq .
w9864g2gh publication release date:jan. 29, 2008 - 16 - revision a10 9.3 capacitance ( vcc = 3.3v0.3v for -5/-6/-6c/-6i , vcc=2.6v-3.6v for -7, t a = 25 c, f = 1 mhz) parameter sym. min. max. unit input capacitance (a0 to a10, bs0, bs1, cs , ras , cas , we , dqm, cke) c i 2.5 4 pf input capacitance (clk) c clk 2.5 4 pf input/output capacitance (dq0 ? dq31) c o 4 6.5 pf note: these parameters are periodically sampled and not 100% tested 9.4 dc characteristics (vcc = 3.3v0.3v for -5/-6/-6 c,vcc=2.6v-3.6v for -7 on t a = 0~70c, vcc = 3.3v0.3v for 6i on t a = -40 ~85 c. ) -5 -6/- 6c/-6i -7 parameter sym. max. max. max. unit notes operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i cc1 110 100 90 3 standby current t ck = min., cs = v ih v ih/l = v ih (min.)/v il (max.) cke = v ih i cc2 40 35 30 3 bank: inactive state cke = v il (power down mode) i cc2p 3 3 3 3 standby current clk = v il , cs = v ih v ih/l =v ih (min.)/v il (max.) cke = v ih i cc2s 15 15 15 bank: inactive state cke = v il (power down mode) i cc2ps 3 3 3 ma no operating current t ck = min., cs = v ih (min.) cke = v ih i cc3 70 65 60 bank: active state (4 banks) cke = v il (power down mode) i cc3p 15 15 15 burst operating current (t ck = min.) read/write command cycling i cc4 150 140 130 3, 4 auto refresh current (t ck = min.) auto refresh command cycling i cc5 170 150 140 3 self refresh current self refresh mode (cke = 0.2v) i cc6 2 2 2
w9864g2gh publication release date:jan. 29, 2008 - 17 - revision a10 9.5 ac characteristics and operating condition (vcc = 3.3v0.3v for -5/-6/-6c,vcc=2.6v-3.6v for -7 on t a = 0~70c, vcc = 3.3v0.3v for 6i on t a = -40~85c.) (notes: 5, 6.) -5 -6/-6i -6c -7 parameter sym min. max. min. max. min. max. min. max. unit notes ref/active to ref/active command period trc 55 60 60 65 active to precharge command period tras 40 100000 42 100000 42 100000 45 100000 active to read/write command delay time trcd 15 18 18 20 ns read/write(a) to read/ write(b) command period tccd 1 1 1 1 tck precharge to active(b) command period trp 15 18 18 20 active(a) to active(b) command period trrd 10 12 12 14 ns write recovery time cl* = 2 cl* = 3 twr 2 2 2 2 tck clk cycle time cl* = 2 10 1000 10 1000 7.5 1000 10 1000 cl* = 3 tck 5 1000 6 1000 6 1000 7 1000 clk high level tch 2 2 2 2 9 clk low level tcl 2 2 2 2 9 access time from clk cl* = 2 6 5.5 6 cl* = 3 tac 4.5 5 5 5.5 11 output data hold time toh 2 2 2 2 11 output data high impedance time thz 2 5 2 6 2 6 2 7 8 output data low impedance time tlz 0 0 0 0 11 power down mode entry time tsb 0 5 0 6 0 6 0 7 transition time of clk (rise and fall) tt 0.5 1 0.5 1 0.5 1 0.5 1 7 data-in-set-up time tds 1.5 1.5 1.5 1.5 10 data-in hold time tdh 1 1 0.8 1 10 address set-up time tas 1.5 1.5 1.5 1.5 10 address hold time tah 1 1 0.8 1 10 cke set-up time tcks 1.5 1.5 1.5 1.5 10 cke hold time tckh 1 1 0.8 1 10 command set-up time tcms 1.5 1.5 1.5 1.5 10 command hold time tcmh 1 1 0.8 1 ns 10
w9864g2gh publication release date:jan. 29, 2008 - 18 - revision a10 ac characteristics and operating condition, continued -5 -6/-6i -6c -7 parameter sym min. max. min. max. min. max. min. max. unit notes refresh time tref 64 64 64 64 ms mode register set cycle time trsc 10 12 12 14 ns exit self refresh to active command txsr 70 72 72 75 ns notes: 1.operation exceeds ?absolute maximum ratings? may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence please refer to "functi onal description" sect ion described before. 6. ac testing conditions parameter conditions output reference level 1.4v output load see diagram below input signal levels (v ih /v il ) 2.4v/0.4v transition time (t t : tr/tf) of input signal 1/1 ns input reference level 1.4v 50 ohms 1.4 v ac test load z = 50 ohms output 30pf
w9864g2gh publication release date:jan. 29, 2008 - 19 - revision a10 7. transition times are measured between v ih and v il . 8. t hz defines the time at which the outputs achieve t he open circuit condition and is not referenced to output level. 9. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1) t ch is the pulse width of clk measured from th e positive edge to the negative edge referenced to v ih (min.). t cl is the pulse width of clk measured from th e negative edge to the positive edge referenced to v il (max.). (2)a.c latency characteristics cke to clock disable (cke latency) 1 t ck dqm to output to hi-z (read dqm latency) 2 dqm to output to hi-z (write dqm latency) 0 write command to input data (write data latency) 0 cs to command input ( cs latency) 0 cl = 2 2 precharge to dq hi-z lead time cl = 3 3 cl = 2 1 precharge to last valid data out cl = 3 2 cl = 2 2 bust stop command to dq hi-z lead time cl = 3 3 cl = 2 1 bust stop command to last valid data out cl = 3 2 cl = 2 bl + t rp t ck + ns read with auto-precharge command to active/ref command cl = 3 bl + t rp cl = 2 (bl+1) + t rp write with auto-precharge command to active/ref command cl = 3 (bl+1) + t rp 10. assumed input rise and fall time (t t ) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter ( the t t maximum can?t be more than 10ns for low frequency application. ) 11. if clock rising time (t t ) is longer than 1ns, (t t /2-0.5)ns should be added to the parameter.
w9864g2gh publication release date:jan. 29, 2008 - 20 - revision a10 10. timing waveforms 10.1 command input timing t c k clk a0-a10 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah
w9864g2gh publication release date:jan. 29, 2008 - 21 - revision a10 10.2 read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a10 bs0, 1 dq valid data-out valid data-out
w9864g2gh publication release date:jan. 29, 2008 - 22 - revision a10 10.3 control timing of input data *dqm2,3="l" clk (word mask) t cmh t cms t cmh t cms dqm0 t cms t cmh t cmh dqm1 dq0 -dq7 dq16 -dq23 dq8-dq15 dq24-dq31 t dh t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh valid data-in valid data-in t dh valid data-in t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t dh t dh t ds t ds t ds t ds dq0 -dq7 clk cke t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in dq24 -dq31 dq16 -dq23 dq8 -dq15 (clock mask) t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t ds t ds valid data-in valid data-in valid data-in t cms
w9864g2gh publication release date:jan. 29, 2008 - 23 - revision a10 10.4 control timing of output data dq0 -dq7 valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t hz t lz t ac t oh t ac open clk (output enable) dqm0 t cmh t cms t cmh t cms t cmh t cms t cmh t cms dqm1 t oh t ac t ac t hz t ac t ac valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh dq8 -dq15 t ac t hz t lz open dq24 -dq31 dq16 -dq23 valid data-out valid data-out t oh t ac t oh t ac t oh t hz t ac t oh t ac t oh valid data-out valid data-out t oh t oh t lz t oh valid data-out valid data-out valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq16 -dq23 t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq24 -dq31 t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq0 -dq7 cke clk t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq8 -dq15 (clock mask) *dqm2,3="l"
w9864g2gh publication release date:jan. 29, 2008 - 24 - revision a10 10.5 mode register set cycle a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a10 bs0,1 register set data next command a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 bs1 a0 bs0 "0" "0" "0" "0" "0" reserved
w9864g2gh publication release date:jan. 29, 2008 - 25 - revision a10 11. operating timing example 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3 ras cas bs1 bs0
w9864g2gh publication release date:jan. 29, 2008 - 26 - revision a10 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb ap* t rcd
w9864g2gh publication release date:jan. 29, 2008 - 27 - revision a10 11.3 interleaved bank read (bur st length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0
w9864g2gh publication release date:jan. 29, 2008 - 28 - revision a10 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) a0-a9 bank #0 idle bank #1 bank #2 bank #3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0
w9864g2gh publication release date:jan. 29, 2008 - 29 - revision a10 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9 a10 bs1 we cas ras cs idle bank #0 bank #1 bank #2 bank #3 bs0 ax4 ax5 ax6 ax7 by0 by1 by2 by3
w9864g2gh publication release date:jan. 29, 2008 - 30 - revision a10 11.6 interleaved bank write (burst length = 8, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a 0-a9 a 10 bs1 we cas ras cs a ctive write write a ctive bank #0 idle bank #1 bank #2 bank #3 a p* a ctive write a p* bs0
w9864g2gh publication release date:jan. 29, 2008 - 31 - revision a10 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t ras t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap* bs0
w9864g2gh publication release date:jan. 29, 2008 - 32 - revision a10 11.8 page mode read/write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q qqqqq dd d d d clk dq cke dqm a0-a9 a10 bs0 we cas ras cs bs1 active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3
w9864g2gh publication release date:jan. 29, 2008 - 33 - revision a10 11.9 auto-precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs bs1 t rc t ras t rp t ras t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 bs0 bx0 bx2 bx1 bx3
w9864g2gh publication release date:jan. 29, 2008 - 34 - revision a10 11.10 auto-precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a 0-a9 a 10 we cas ras cs bs1 t rc t rc t rp t ras t rp raa t rcd t rcd rab rac raa rab cax rac bx0 bx1 bx2 bx3 a ctive a ctive write a p* a ctive write a p* * ap is the internal precharge start bank #0 idle bank #1 bank #2 bank #3 t ras bs0 caw aw0 aw1 aw2 aw3
w9864g2gh publication release date:jan. 29, 2008 - 35 - revision a10 11.11 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9 a10 we cas ras cs bs0,1
w9864g2gh publication release date:jan. 29, 2008 - 36 - revision a10 11.12 self refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t xsr no operation / command inhibit self refresh exit
w9864g2gh publication release date:jan. 29, 2008 - 37 - revision a10 11.13 bust read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 qq q q d d dq q q q t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3
w9864g2gh publication release date:jan. 29, 2008 - 38 - revision a10 11.14 power down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the power down mode. when cke goes high, command input must be no operation at next clk rising edge. violating refresh requirements during power-down may result in a loss of data. clk dq cke dqm a0-a9 a10 bs we cas ras cs read
w9864g2gh publication release date:jan. 29, 2008 - 39 - revision a10 11.15 auto-precharge timing (write cycle) act 01 3 2 (1) cas latency = 2 (a) burst length = 1 dq 45 7 6891 1 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk
w9864g2gh publication release date:jan. 29, 2008 - 40 - revision a10 11.16 auto-precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w9864g2gh publication release date:jan. 29, 2008 - 41 - revision a10 11.17 timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict. read write 11 10 9 8 7 6 5 4 3 2 1 read read read write write d0 d1 d2 d3 write dq dq ( a ) command 0 dq dq dqm ( b ) command dqm ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 (1) cas latency=2 ( a ) command (2) cas latency=3 in the case of burst length = 4 11.18 timing chart of write to read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0
w9864g2gh publication release date:jan. 29, 2008 - 42 - revision a10 11.19 timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 11.20 timing chart of burst st op cycle (precharge command) 01 11 1098765432 (1) read cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg read (b) cas latency =3 command q0 q1 q2 q3 q4 prcg read dq dq (2) write cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg write (b) cas latency =3 command q0 q1 q2 q3 q4 write dq dq dqm dqm prcg twr twr
w9864g2gh publication release date:jan. 29, 2008 - 43 - revision a10 11.21 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w9864g2gh publication release date:jan. 29, 2008 - 44 - revision a10 11.22 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk
w9864g2gh publication release date:jan. 29, 2008 - 45 - revision a10 12. package specification 12.1 86l tsop (ii)-400 mil seating plane e d a2 a1 a b zd 1 43 86 44 e h e y l c l1 q zd 0.61 0.024 0.002 0.007 max. min. nom. a2 b a a1 0.17 1.00 0.05 0.27 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.50 0.020 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.011 0.047 0.006 dimension (inch) l1 0.80 0.032 c 0.12 0.005 0.455 11.76 11.56 11.96 0.463 0.471 h e y 0.10 0.004 controlling dimension: millimeters 0.21 0.008
w9864g2gh publication release date:jan. 29, 2008 - 46 - revision a10 13. revision history version date page description a01 jul. 05, 2006 all create new datasheet a02 aug. 03, 2006 3,14,15,16 add ?6c grade a03 aug. 07, /2006 15,16 modify i cc1 , i cc4 , i cc5 & transition time of clk a04 oct. 03, 2006 16 add t xsr timing specification. a05 nov. 13, 2006 3,13,14 modify t ih =0.8ns in ?6c grade a06 jan. 11, 2007 16,18 modify ac characteristics notes 10 and add notes 11 (t t ) a07 apr. 10, 2007 3,14,15,16 add -6i for t a = -40~85c a08 jul. 19, 2007 14 add output leakage current io(l) specification. a09 aug. 13, 2007 18,19 revise transient time t t ac test condition and calculate formula for compensation consideration in notes 6, 10 of ac characteristics and operating condition a10 jan. 29, 2008 3,15,16,17 change -7 grade power supply voltage from 2.7v-3.6v to 2.6v-3.6v important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, at omic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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